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Pentek Model 6526 Operating Manual Page 11

Rev. A

Chapter 1: Overview

1.1 Introduction

The Model 6526 is a 16−Channel, two input, Narrowband Digital Receiver for the

VMEbus. It features a RACEway

™

interface for output data, and several on−board

control sections for supporting input switching, multi−board synchronization, and

time code stamping of data. The Model 6526 is a single−slot, 6U VME board with front

panel connections for input clock, input data, and synchronization signals. It includes

a 32−bit VMEbus slave interface for control and status.

The RACEway interface allows packets of data from each receiver channel to be

directed to different RACEway−equipped VME boards, including memory and DSP

functions. RACEway is a high−speed, synchronous backplane bus capable of deliver−

ing 32−bit word transfers between VME boards at a peak rate of 160 MB/sec. It offers

significant advantages for VMEbus systems by providing a high−speed data channel

completely independent of the VMEbus. The interface utilizes the 64 user−defined

pins of the VME P2 connector, which are usually unconnected pins in most backplanes.

1.2 Digital Receiver

The Model 6526 uses four Graychip GC4014 Quad Narrowband Digital Drop Receivers

(DDRs) to provide a total of 16 receiver channels. Two front panel parallel digital data

inputs operate at either TTL or differential ECL logic levels, and support up to 16 bits of

data and one clock at sampling rates up to 62.5 MHz for ECL and 50 MHz for TTL. The

clock for the two inputs must be the same to meet the timing requirements of the

GC4014’s. The front panel inputs are directly compatible with the digital output of

Pentek's Series 64xx A/D Converters.

The two parallel input signals are connected to two 16−bit inputs of each GC4014.

Within the GC4014, input crossbar switches allow any DDR channel to independently

select either of the two input signals. The GC4014’s are controlled by commands from

the VMEbus and by an on−board TMS320C31 DSP (Digital Signal Processor) for setting

all operational parameters of the receiver channels.

1.3 Synchronization

The front panel of the Model 6526 has a Sync bus that can be bridged across all Model

6526’s in a system. It is used to distribute four synchronization signals to all connected

boards for synchronizing each of the of the same−channel DDR sections on each board.

An on−board Sync Generator controlled by VMEbus commands can generate any

number of sync signals (1 to 4) for output to the Sync bus.

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VXI?Corporation F80 Spezifikationen Seite 11