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Page 8 Pentek Model 6526 Operating Manual
Page
Table of Contents
Rev. A
Chapter 3: Memory Maps and Register Descriptions (continued)
3.6.12 Channel n RACEway Routing Register ......................................................................... 83
Table 3−42: Channel n RACEway Routing Register ................................................. 83
3.6.12.1 Mode Selection............................................................................................... 83
3.6.12.2 Routing Priority Code................................................................................... 83
Table 3−43: RACEway Routing Register − Priority Codes................... 84
3.6.12.3 Broadcast Accept Code ................................................................................. 84
3.6.12.4 RACEway Route Fields ................................................................................ 85
Table 3−44: RACEway Routing Register − Route Field Exit Codes .. 85
3.6.13 Channel n RACEway Start Address Register ...........................................................................86
Table 3−45: Channel n RACEway Start Address Register ....................................... 86
3.6.13.1 Lock Flag......................................................................................................... 86
3.6.13.2 Read Flag ........................................................................................................ 86
3.6.13.3 Start Address Fiel ......................................................................................... 87
3.6.13.4 Width/Alignment Field .............................................................................. 87
3.6.14 Channel n RACEway End Address Register .............................................................................88
Table 3−46: Channel n RACEway End Address Register ........................................ 88
3.6.14.1 End Address Field ......................................................................................... 88
3.6.14.2 RACEway Address Mod .............................................................................. 90
3.7 Dual Port Memory and Command Tables ..................................................................................... 91
Table 3−47: Dual Port SRAM Usage Memory Map.................................................................... 91
Table 3−48: Command Table Header Words Memory Map ..................................................... 93
Table 3−49: Command Table Start Addresses............................................................................. 93
3.7.1 Command Table Header Word #1: Command Control ............................................. 94
Table 3−50: Command Table Header Word #1: Command Control....................... 94
3.7.1.1 Single Load ..................................................................................................... 94
3.7.1.2 Schedule Command ...................................................................................... 94
3.7.1.3 Command Table Length............................................................................... 95
3.7.1.4 Data Format.................................................................................................... 95
Table 3−51: Command Table Header Word 1 − Data Format .............. 95
3.7.2 Command Table Header Word #2: Channel Mask....................................................... 96
Table 3−52: Command Table Header Word #2: Channel Mask .............................. 96
3.7.3 Command Table Header Word #3: Timestamp............................................................ 96
Table 3−53: Command Table Header Word #3: Timestamp .................................... 96
3.7.4 Command Table Header Word #4: Command Status ................................................. 97
Table 3−54: Command Table Header Word #4: Command Status ......................... 97
3.7.4.1 Command Complete..................................................................................... 97
3.7.4.2 Command Error............................................................................................. 97
3.7.4.3 Command Parameter Error.......................................................................... 97
3.7.4.4 Command Error Location ............................................................................ 97
3.7.5 Command Set .................................................................................................................... 98
3.7.6 'C' Callable Library Functions ........................................................................................ 98
- PENTEK MODEL 6526 1
- Copyrights 2
- Trademarks 2
- Manual Revision History 2
- Warranty 2
- Table of Contents 10
- Chapter 1: Overview 11
- 1.6 Channel Formatters 12
- 1.4 Time Stamp Counter 12
- 1.5 Command Controller / DSP 12
- 1.7 RACEway Interface 13
- 1.8 Digital Interfaces 13
- 1.9 VMEbus Interface 13
- 1.10 Model 6526 Block Diagram 14
- 1.11 Specifications 15
- 2.1 Inspection 17
- Pin 1 – Pin 2* Disabled* 22
- Pin 2 – Pin 3 Enabled 22
- * Factory Default Setting 22
- 2.4 Model 6526 Front Panel 23
- 2.4.2 Sync Bus 27
- 2.4.2.1 Sync Bus Connector 27
- 2.4.2 Sync Bus (continued) 28
- 2.4.3 TMS320C31 Serial Port 31
- 2.4.4 Reset Button 31
- CAUTION!! 33
- 3.1 Programming Overview 35
- 3.3 VMEbus Access 36
- 3.4 VMEbus A16 Slave Memory 37
- 3.4.1.2 DSP Reset − Bit D1 38
- 3.6.13.1 Lock Flag − Bit D0 86
- 3.6.13.2 Read Flag − Bit D1 86
- 3.7.1.1 Single Load − Bit D0 94
- 3.7.5 Command Set 98
- (continued) 100
- 3.8.1.1 BIST Fail − Bit D0 103
- 3.8.1.2 DSP LED − Bit D9 103
- Sync_Source bit SYNC 107
- B.1 Overview 133
- B.2 RACEway ILK1 133
- B.3 RACEway ILK 4 Example 133
- B.4 RACEway ILK 8 Example 134
- B.5 RACEway ILK12 Example 136
- B.6 RACEway ILK16 Example 137
- Appendix C: Graychip 4014 139
- Rev.: A 140
- GRAYCHIP 141
- “NARROW*1.97” 142
- “NARROW*0.97 + 1" 142
- GC4014 DATASHEET 146
- 3.0 FUNCTIONAL DESCRIPTION 147
- 3.1 CONTROL INTERFACE 147
- READ CYCLE- RD HELD LOW 148
- WRITE CYCLE- RD 148
- HELD LOW 148
- 3.3 THE DOWN CONVERTERS 149
- Figure 4. NCO Circuit 150
- Figure 5. Example NCO Spurs 150
- 3.3.2 Four Stage CIC Filter 151
- 3.3.3 Coarse Channel Gain 152
- (c) GSM Coefficients 153
- ∞ to +24 dB in 154
- 3.6 OUTPUT MODES 155
- 3.6.2 Serial Outputs 155
- Table 2: TDM Modes 155
- 3.6.3 Link Mode Output 156
- 3.7 CLOCKING 157
- 3.8 POWER DOWN MODES 157
- 3.9 SYNCHRONIZATION 157
- 3.10 DATA LATENCY 158
- 3.11 DIAGNOSTICS 158
- Table 3: Latency 158
- 4.0 PACKAGING 159
- GC4014-PQ 159
- QUAD RCVR 159
- MMMMMM LLL 159
- GRAYCHIP YYWW 159
- 5.0 CONTROL REGISTERS 161
- 5.1 SYNC MODE REGISTER 162
- Table 4: Sync Modes 162
- 5.2 DECIMATION MODE REGISTER 163
- 5.3 CIC DECIMATION REGISTERS 163
- 5.4 SCALE CONTROL REGISTER 164
- 5.5 CHANNEL GAIN REGISTER 164
- 5.6 OUTPUT FORMAT REGISTER 165
- 5.7 OUTPUT MODE REGISTER 165
- 5.8 BLANKING CONTROL REGISTER 165
- 5.10 COUNTER MODE REGISTERS 166
- 5.11 TEST MODE REGISTER 167
- 5.12 PAGE MAP REGISTER 167
- 5.13 STATUS CONTROL REGISTER 168
- 5.14 CHECKSUM REGISTER 168
- Table 5: Mask Revisions 169
- , suggested default = 0x80 170
- , suggested default = 0x5f 171
- 6.4 DC CHARACTERISTICS 174
- 6.5 AC CHARACTERISTICS 175
- GSM Blocker Requirements 177
- Table 11: GSM Configuration 178
- DAMPS Blocker Requirements 179
- PFIR_SUM 180
- 7.7 DIAGNOSTICS 181
- 7.8 OUTPUT TEST CONFIGURATION 183
- SCALE 6 BIG_SCALE× 56–+() 184
- Appendix D: PitCREWjr 185
- Master Writes and Slave Reads 187
- Master Reads and Slave 187
- Figure 2 189
- Master Function 189
- Figure 4 190
- Figure 5 190
- Figures 6 190
- Figure 5. Master Read 191
- Figure 6. Slave Write 191
- Figure 8 192
- Figure 9 192
- Figure 10 192
- Figure 9. SRE Function 194
- Figure 10. Master Read Error 195
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