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Pentek Model 6526 Operating Manual Page 15

Rev. A

1.11 Specifications

Receiver Chips: 4 (four) Graychip GC4014s, 16−bit input data

(See Appendix C for chip specifications)

Digital Inputs

Input Connectors: Front panel 80−pin 3M connector for 0.025" pitch cable;

accepts two input signals of up to 16 data bits each, using

80−conductor cable (3M # 3756/80, Pentek # 378.68000) &

80−pin connector (3M # 82080−6006, Pentek # 353.08005)

Option 002: Differential ECL inputs compatible with Pentek Models

6402−002, 6410−002, 6441−002, and 6465 A/D Converters

(using Pentek’s Model 2117 cable assembly), and Pentek

Models 6425−001, 6470, and 6472 A/D Converters (using

Pentek’s Model 2119 cable assembly); these A/D

Converters can provide data rates up to 70 MHz

Option 019: Single−ended TTL inputs compatible with Pentek Models

4261−019, 6402, 6410, 6420, 6421, and 6441 (using Pentek’s

Model 2117 cable assembly), and Pentek Model 6425 (using

Pentek’s Model 2119 cable assembly); data rates up to

41 MHz can be provided by these units

Input Signals (2):

Data:

16 (sixteen) bit lines/input signal

(16 differential pairs (32 lines) for Option 002)

Clock: 1 (one) bit line/input signal

Clock Rate: 62.5 MHz, maximum (Option 002)

50 MHz, maximum (Option 019)

External Sync:

2 (two) bit lines/input (filter & accumulator syncs)

Data Setup Time: 2 nsec before rising edge of clock

Data Hold Time: 2 nsec after rising edge of clock

Input Multiplexers: Each receiver can independently select Input A or Input B

Input FIFO Memory:

4k x 32 Synchronous FIFO for each receiver

RACEway Interface: One PitCREWjr chip set; transfers data at 160 MByte/sec

peak and 140 MByte/sec sustained throughput

(See Appendix D for chip specifications)

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